Product Line Managers and ASIC Program Managers face the same fundamental problem: mixed-signal ASIC part prices may be affordable, but up-front costs are such that the total cost of ownership only makes sense for products that run in high volume. What if your market is slow to start?

A variety of options exists today, ranging from virtually zero Non-Recurring Engineering (NRE) cost, high component price Field Programmable Gate Arrays (FPGAs), to low NRE Structured ASIC, to lowest component cost but high NRE full mixed-signal Standard Cell ASIC. All of these options solve one or two of the problems identified above, but not all.

FPGAs offer the lowest barrier to entry. Attractions include low starting costs, on-the-fly field programmability, and decent performance. Newer FPGAs even include fast interfaces and other IP blocks that can help speed up development. In truly high volume, however, field programmability is typically no longer required, and the additional component expense becomes a significant barrier to profitability. Conversion to an ASIC is possible, as long as this path is planned for well in advance and the design does not use any of the proprietary IP offered by the FPGA vendors, since such IP is typically not available for porting to other silicon.

Structured ASIC, Platform ASIC, and a variety of similar technologies offer configurability through metal layers. NRE costs are higher than for FPGA, but substantially lower than for a full mixed-signal Standard Cell ASIC. Product changes can be made very quickly. Component size and therefore price, although much better than FPGA, is still not optimal, once again presenting a barrier to profitability when volume increases.

Mixed-signal Standard Cell ASIC or custom ASIC solutions offer the best performance and the smallest die size, but also require a significant up-front NRE investment that can range from hundreds of thousands to millions of dollars. In addition, mask preparation and production are time consuming, which slows down product market entry and increases the risk that requirements could change between product definition and market introduction.

Most smaller companies, or new product lines in large companies, have to start development with limited funds. The new product has to prove itself before additional funding will become available, either from investors or the parent company. Yet when the product becomes successful, features ultimately take a back seat to simple concerns of low component cost.

In the following pages, we present two development approaches that significantly reduce the time it takes to introduce a new mixed-signal ASIC and that increase the chances of having the right feature set for the market at the lowest cost.

Design Application and Development Requirements

The design objective of the mixed-signal ASIC was to facilitate the seamless connection of multiple PC displays of different resolutions and types via USB to a host computer running Windows. The customer uses the new mixed-signal ASIC, in conjunction with a virtual Graphics Card implemented in software, to process a pixel stream into a proprietary graphics transport format, and to then transmit that data over a High Speed USB 2.0 link for display on a standard screen.

Applications include cloning or extending a desktop onto one or more additional displays. These additional screens can either display the same information as the main screen, or show completely different applications. The mixed-signal chip can also be used as part of a USB video hub or part of a USB laptop docking station. This device was successfully demonstrated by the customer at a major consumer electronics show in 2007, and is now in volume production.

In order for multiple displays to operate without perceptible degradation in performance, the mixed-signal ASIC required a fully compliant USB 2.0 high-speed interface, with a USB device controller and a small 8-bit host processor. An additional requirement for imperceptible latency drove the need for a DDR (Double Data Rate) SDRAM memory interface for frame buffering.

There are a wide variety of video data speeds needed to communicate with screens of different resolution and refresh rates, so there was a need for a flexible clocking scheme allowing different frequencies to be generated and adjusted in order to avoid restricting the application of the device. Different I/O standards were also required, to allow communication of video data to different types of displays.

In addition to the technical requirements of the mixed-signal ASIC itself, the customer did not have a full set of ASIC development tools available during the project. The ASIC vendor was required to demonstrate a flexible approach to the design flow and breakdown of design work to reduce both engineering time and capital outlay for design tools.

The main features required for the ASIC are shown in the block diagram in Figure 1.

Many ASIC engineers incorporate an FPGA validation phase in their product development. Despite the many attractions of FPGA, it’s easy to fall into the trap of using easily accessible, yet proprietary, IP and various built-in structures such as multipliers, necessary to overcome the inherent FPGA performance limitations. This paper helps to avoid these pitfalls, and thus helps to create a smooth FPGA to mixed-signal ASIC migration for volume production.

Design Migration

Designing with FPGAs is relatively straightforward. Basic tools and hardware platforms are available to the developer for little or no money, so the design environment is easy to set up. The problem with using FPGA for mixed-signal ASIC prototyping has been the inability to include Physical IP that is not supported by the FPGA vendor.

Typically, the FPGA vendor solves this problem in one of two ways: first, a very high-end part is offered that includes IP with functionality similar to the desired IP, or second, a hardware platform that includes discrete components to make up for the lack in functionality in the FPGA is developed.

The first method forces the use of expensive parts; with the second method, it is no longer possible to verify the entire design using re-programmable parts. Specifically, an additional step in the mixed-signal ASIC integration cycle is required when migrating from an FPGA, because the designer needs to replace the physical IP or external interface and redesign logic as a result. The option to test the newly integrated RTL only exists in the final ASIC, requiring metal fixes or even a re-spin should anything go wrong. Also, most FPGAs contain substantial amounts of tempting, proprietary digital IP and structures, which are not available for use with technologies from other vendors.

The inability to include physical IP not supported by the FPGA vendor, and the FPGA containing proprietary IP and built-in structures introduces two painful realities: The design is no longer easily portable to a mixed-signal ASIC. The final product requires re- testing and re-verification to ensure any IP used to replace the FPGA structures works properly. ASIC companies have introduced hardware tools that alleviate the problems of IP portability, specifically for PHY IP. Using these platforms, designers can benefit from the speed and agility of FPGA prototyping, and in addition, they can design with the same PHY IP from the development stage through to final silicon. A typical ASIC Kit consists of two main components: A hardware platform, containing both a standard FPGA (for logic development), and test silicon containing the physical IP intended for future integration, and a software suite and library. 

Types of Integration

There are essentially three levels of production that you can design for—low, medium, and high volume.

Field programmable gate arrays (FPGAs) are typically best suited for prototypes and low volume production, either with an internal PHY or with a recommended external third party PHY. Start-up costs of FPGA are very low, and parts can be purchased in single quantities. There are integration issues with FPGAs, and the path to volume production can be complex (also see ChipX white paper: Prototyping Physical Layer IP ASIC with FPGA).

If medium to high volume is expected, development can still take place using an FPGA, with a migration to an Application Specific Standard Product (ASSP) PCIe bridge or Mixed-signal ASIC. With a bridge chip, the end result will have surplus silicon, but the bridge chip is also the easiest solution for achieving volume production. If a chip has all the functionality and performance you need, simply buy it off the shelf!

Another medium to high volume solution is Mixed-signal ASIC. ASICs provide the exact functionality and performance you need, without sacrificing development time or introducing design risk. ASICs also provide a completely seamless path from prototype to production. For solutions where high volume production is expected from the outset, Standard Cell ASIC solutions are best. The upfront risk is much higher and time to market is much longer, but after the chip is in production, costs are lowest.

The Integration Process

The following integration process is simplified for purposes of this overview:

1.Select a PHY transceiver (or PHY IP, if you are going to develop on silicon) and Controller IP.

2.Integrate these IP blocks in the technology and design of choice.

3.Where applicable, make a test chip and PCB. Conduct lab tests

To take a new product from the drawing board to the shelves can take several years, and during that time, the product specifications are likely to have changed several times.

This scenario puts a lot of pressure on system architects and business managers, particularly if they are basing their design upon a large mixed-signal ASIC. The paper presents a method for system architects to decrease design risk and increase design success. Examples of applications are given.

In an ideal world, the period from product conception to delivery would be limited to a matter of months, markets would be monolithic, and designers would have a clear and complete picture of consumers’ requirements from day one. This is far from being a true representation of what actually happens. To take a new product from the drawing board to the shelves can take several years, and during that time, the product specifications are likely to have changed several times. Further, when the product is finally launched, it is very likely that its intended market—far from being monolithic—has fractured into several smaller segments, all requiring slightly different end product functionality. This problem has worsened in the past decade, with the trend toward system integration, ASICs growing to well over ten million gates, and specifications being frozen two to three years before market introduction.

This scenario puts a lot of pressure on system architects and business managers, particularly if they are basing their design upon a large ASIC. To keep costs down, they must keep the design tight and avoid multiple chip iterations. However, to retain flexibility and address as much of the final available market as possible (thus ensuring that enough units can be sold to justify using a full Standard Cell architecture in the first place), they will need to build in functions that not all customers will require.

The Flexibility of the SideChip Approach

The System-on-Chip (SoC) trend of the past does not scale well into the next decade.

Perhaps a better approach might be one of integration in moderation. By partitioning a system into two chips—one a large, Standard Cell ASIC that contains all the core system functionality easily identifiable at a project’s outset, and the other a smaller, mixed-signal ASIC that delivers the value-added features and standards-dependent functions—designers can get to market faster and retain system agility, enabling them to address multiple segments of a fragmented market.

We suggest that companies who choose this approach can introduce new product generations and variations faster, while benefiting from significantly engineering reduced risk.

Under this new design flow, system architects might partition a design into a 5- or 10- million gate Standard Cell ASIC, with an accompanying SideChip mixed-signal ASIC containing, perhaps, 500,000 gates. The main ASIC would be stripped down to contain only those functions central to the requirements of the system. This means the main ASIC is much simpler to design and less dependent on end-market requirements, thus reducing the risk of having to re-spin the chip. Extra functions can be identified in as few as nine months before the product launch date. As an example, the SideChip could contain mixed-signal standards–based subsystems that need up-to-date compliance testing, such as USB 2.0.