The CX5000 Structured ASIC family is based on 0.18µ technology using 3 layers of programmable metal, and supports performance levels up to 200 MHz. The 0.18µ CX5000 is a Structured ASIC that utilizes the combination of advanced metal programmable gate array technology and an optimized EDA system to implement high performance ASIC designs while reducing application tooling costs and design turnaround time. ASIC designers using the CX5000 are able to meet or exceed their design schedules and budgets without compromising technical objectives.

Key Features

• 30K to 1.1M usable ASIC gates
• Up to 2.6M bits of fast block memory
• 2ns access time single-port/dual-port SRAM and ROM
• Configurable I/O: PCI, PCI-X, SSTL, HSTL, USB FS, RSDS, LVTTL, LVCMOS, LVPECL and LVDS up to 622Mbps as well as Power & Ground
• Up to 1,152 total pads
• 200MHz general core logic operation, 500MHz in constrained clock domains
• 1.5V or 1.8V or mixed supply voltage operation
• 4 Low-jitter APLLs macro with internal loop filter
• 3-4 week lead time for tested prototypes